a trouble in code_gen

[jsjcsq]

hi,everyone.
i have a question in code_gen.v,which used to generate early ,prompt ,late code . i think lpm_shiftreg driven by the 40M clock,lead to the three types code only 1/40M separate,but this made the result wrong .could anyone tell me the correct answers.thanks .

[mumford]

Hi jsjcsq

The version of the code_gen you should use is "code_gen2.v"
In this version of the code there is no lpm based shiftreg, as the following code excerpt shows:

always @(posedge clk)
begin
if (prn_key_enable)
srq <= 3'b0;
else if (hc_enable)
begin
srq[0] <= ca_code;
srq[2:1] <= srq [1:0];
end
end

Here the hc_enable drives the shifting process. This is the "half-chip" enable that runs at (you guessed it) the half chip rate.

Hope this helps.