Welcome to the Namuru GPS receiver technical reference page.
For information on the Namuru I L1 receiver platform, please
For information on the Namuru II L1/L2 receiver platform, please
In 2003 a project to build a GPS receiver using an FPGA to provide the core digital functions was started at the University of New South Wales Satellite Navigation and Positioning Laboratory (SNAP) and National ICT Australia (NICTA).
The outcome of this work is a GPS receiver dubbed the "NAMURU", which is a slight variation of the Aboriginal word "ngamuru" that means to follow a path or to navigate. In this case the name NAMURU was chosen because it stands for Navigational Apparatus Made at UNSW for Reconfiguration by Users.
Technical research papers relating to this work have been published and presented at various conferences during the development of the project. You can download copies from this site HERE
The GPS Receiver shown in the picture is the Namuru V1 platform intended for Global Positioning System (GPS) receiver research and development. This fully functional GPS receiver design can provide 12 or more channels of parallel tracking hardware and software.
V1A Receiver board with down converter RF shield cover removed.
All receiver baseband signal processing functions and CPU are embedded in an Altera FPGA. The complete receiver is built on a custom designed 8 layer printed circuit board. Outputs from the board are available through a group of interface options.
As a starting point for a developer, the receiver operates as a 12 channel 'All-in-View' GPS receiver which can be used as a reference design and modified as required to develop a new receiver.
The receiver reference design is available in 4 parts:
- The receiver board itself
- The source code for the FPGA logic supplied in Verilog HDL.
- The source code of the GPS software for acquiring and tracking satellites supplied in C.
- The Quartus II projects to bundle it all together using the PC based software development tools supplied by Altera.
- GPS functions in FPGA with spare capacity for further development
- NIOS II 32 bit soft core CPU
- spare IO pins
- LEDS for diagnostic & debugging
- System reset and power monitor
- Battery backed real time clock
- Battery backed SRAM to store almanac
- HDL source code for logic in Verilog
- C soirce code for acquisition, tracking, and navigation software
THE DEVELOPMENT TEAM
The receiver development engineers in the SNAP Laboratory at UNSW, testing the receiver on the
Spirent GPS simulator. From the left Kevin Parkinson, Peter Mumford and Frank Engel.
This work is supported by the University of New South Wales and National ICT Australia under the direction of Prof. Chris Rizos and Prof. Andrew Dempster at the UNSW SNAP Laboratory.